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| rev. 0.5 / sep 2007 1 this document is a general product de scription and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are implied. hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 1gb ddr3 sdram (preliminary version) hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp ** since ddr3 specification has n ot been defined completely yet in jedec, this document may contain items under discussion. ** contents may be changed at any time without any notice. ** part number may also be changed by the result of nomenclature revision in progress.
rev. 0.5 /sep 2007 2 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp revision history revision no. history draft date remark 0.1 preliminary 2007-4 0.2 editorial changed 2007-5 0.3 editorial added 2007-5 0.4 editorial changed 2007-8 0.5 editorial changed 2007-9 rev. 0.5 /sep 2007 3 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp table of contents 1. description 1.1 device features and ordering information 1.1.1 description 1.1.2 features 1.1.3 ordering information 1.1.4 ordering frequency 1.2 package ballout 1.3 row and column address table : 512m/1g fixed 1.4 pin functional description 2. command description 2.1 command truth table 2.2 clock enable (cke) truth table for synchronous transitions 3. absolute maximum ratings 4. operating conditions 4.1 operating temperature condition 4.2 dc operating conditions 5. ac and dc input measurement levels 5.1 ac and dc logic input levels for single-ended signals 5.2 ac and dc logic input levels for differential signals 5.3 differential input cross point voltage 5.4 slew rate definitions for single ended input signals 5.4.1 input slew rate for input setup time (tis) and data setup time (tds) 5.4.2 input slew rate for input hold time (tih) and data hold time (tdh) 5.5 slew rate definitions for differential input signals rev. 0.5 /sep 2007 4 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 6. ac and dc output measurement levels 6.1 single ended ac and dc output levels 6.1.1 differential ac and dc output levels 6.2 single ended output slew rate 6.3 differential output slew rate 6.4 reference load for ac timing and output slew rate 7. overshoot and undershoot specifications 7.1 address and control overshoot and undershoot specifications 7.2 clock, data, strobe and mask ov ershoot and undershoot specifications 7.3 34 ohm output driver dc electrical characteristics 7.4 output driver temperature and voltage sensitivity 7.5 on-die termination (odt) levels and i-v characteristics 7.5.1 on-die termination (odt) levels and i-v characteristics 7.5.2 odt dc electrical characteristics 7.5.3 odt temperature and voltage sensitivity 7.6 odt timing definitions 7.6.1 test load for odt timings 7.6.2 odt timing reference load 8. idd specification parameters and test conditions 8.1 idd measurement conditions 8.2 idd specifications 8.2.1 idd6 current definition 8.2.2 idd6tc specification (see notes 1~2) 9. input/output capacitance 10. standard speed bins 11. electrical characteristics and ac timing 12. package dimensions rev. 0.5 /sep 2007 5 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 1. description preliminary the hy5tq1g431znfp, hy5tq1g831znfp and hy5tq1g 631znfp are a 1,073,741,824-bit cmos double data rate iii (ddr3) synchronous dram, ideally suited for the main memory applications which requires large memory density and high bandwidth. hynix 1gb ddr3 sdrams offer fu lly synchronous operations referenced to both rising and falling edges of the clock. while all addresses and control inpu ts are latched on the rising edges of the ck (falling edges of the ck), data, data strobes and wr ite data masks inputs are sampled on both rising and falling edges of it. the data paths are internally pipelined and 8-bi t prefetched to achieve very high bandwidth. 1.1 device features and ordering information 1.1 . 1 features ? vdd=vddq=1.5v +/- 0.075v ? fully differential clock inputs (ck, /ck) operation ? differential data strobe (dqs, /dqs) ? on chip dll align dq, dqs and /dqs transition with ck transition ? dm masks write data-in at the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? programmable cas latency 5, 6, 7, 8, 9, 10, and (11) supported ? programmable additive latency 0, cl-1, and cl-2 supported ? programmable cas write latency (cwl) = 5, 6, 7, 8 ? programmable burst length 4/8 with both nibble sequential and interleave mode ? bl switch on the fly ? 8banks ? 8k refresh cycles /64ms ? jedec standard 78ball fbga(x4/x8) , 96ball fbga(x16) ? driver strength selected by emrs ? dynamic on die termination supported ? asynchronous reset pin supported ? zq calibration supported ? tdqs (termination data strobe) supported (x8 only) ? write levelization supported ? auto self refresh supported ? on die thermal sensor supported ( jedec optional ) ? 8 bit pre-fetch 1.1 . 2 ordering information * x means binning gr ade (speed/idd...) part no. configuration package hy5tq1g431znfp-x* 256m x 4 82ball fbga hy5tq1g831znfp-x* 128m x 8 hy5tq1g631znfp-x* 64m x 16 100ball fbga 1.1 . 3 operating frequency -tbd grade frequency [mhz] remark (cl-trcd-trp) cl5 cl6 cl7 cl8 cl9 cl10 -s5 ddr3-800 5-5-5 -s6 ddr3-800 6-6-6 -g6 ddr3-1066 6-6-6 -g7 ddr3-1066 7-7-7 -g8 ddr3-1066 8-8-8 -h7 ddr3-1333 7-7-7 -h8 ddr3-1333 8-8-8 -h9 ddr3-1333 9-9-9 -p8 ddr3-1600 8-8-8 -p9 ddr3-1600 9-9-9 -p1 ddr3-1600 10-10-10 rev. 0.5 /sep 2007 6 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 1.2 package ballout 1 2 3 4 5 6 7 8 9 10 11 a nc nc nc nc nc nc b c nc nc nc nc nc nc d e f nc vss vdd nc nu/tdqs# vss vdd nc a g vss vssq dq0 dm/tdqs vssq vddq b h vddq dq2 dqs dq1 dq3 vssq c j vssq dq6 dqs# vdd vss vssq d k vrefdq vddq dq4 dq7 dq5 vddq e l nc vss ras# ck vss nc f m odt vdd cas# ck# vdd cke g n nc cs# we# a10/ap zq nc h p vss ba0 ba2 a15 vrefca vss j r vdd a3 a0 a12/bc# ba1 vdd k t vss a5 a2 a1 a4 vss l u vdd a7 a9 a11 a6 vdd m v nc vss reset# a13 a14 a8 vss nc n w y aa nc nc nc nc nc nc ab ac nc nc nc nc nc nc 1 2 3 4 5 6 7 8 9 1234 89 567 a b c d e f g h j k l mo-207 variation dt-z (x8) n m 1234 89 567 a b c d e f g h j k l mo-207 variation dw-z (x8) n m 10 11 p r t u v w x aa ab ac with support balls note1. green nc balls indicate mechanical support balls with no internal connection any of the support ball locations may or may not be populated with a ball populated ball ball not populated rev. 0.5 /sep 2007 7 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 1.3 row and column address table 1gb 2gb 4gb 8gb note1 : page size is the number of bytes of data delive red from the array to the internal sense amplifiers when an active command is regi stered. page size is per bank, calculated as follows: page size = 2 colbits * org 8 where colbits = the number of column address bits, org = the number of i/o (dq) bits configuration 256mb x 4 128mb x 8 64mb x 16 # of banks 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a10/ap a10/ap a10/ap bl switch on the fly a12/bc# a12/bc# a12/bc# row address a0 - a13 a0 - a13 a0 - a12 column address a0 - a9,a11 a0 - a9 a0 - a9 page size 1 1 kb 1 kb 2 kb configuration 512mb x 4 256mb x 8 128mb x 16 # of banks 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a10/ap a10/ap a10/ap bl switch on the fly a12/bc# a12/bc# a12/bc# row address a0 - a14 a0 - a14 a0 - a13 column address a0 - a9,a11 a0 - a9 a0 - a9 page size 1 1 kb 1 kb 2 kb configuration 1gb x 4 512mb x 8 256mb x 16 # of banks 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a10/ap a10/ap a10/ap bl switch on the fly a12/bc# a12/bc# a12/bc# row address a0 - a15 a0 - a15 a0 - a14 column address a0 - a9,a11 a0 - a9 a0 - a9 page size 1 1 kb 1 kb 2 kb configuration 2gb x 4 1gb x 8 512mb x 16 # of banks 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a10/ap a10/ap a10/ap bl switch on the fly a12/bc# a12/bc# a12/bc# row address a0 - a15 a0 - a15 a0 - a15 column address a0 - a9, a11, a13 a0 - a9, a11 a0 - a9 page size 1 2 kb 2 kb 2 kb rev. 0.5 /sep 2007 8 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 1.4 pin functional description input / output func tional description symbol type function ck, ck# input clock: ck and ck# are differential clock inpu ts. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. cke input clock enable: cke high activates, and cke low de activates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self- refresh operation (all banks idle), or active power-down (row active in any bank). cke is asynchronous for self-refresh exit. af ter vrefca and vrefdq have become stable during the power on and initia lization sequence, they must be maintained during all operations (including self-refresh). cke must be maintained high throughout read and write accesses. input buffers, exclud ing ck, ck#, odt and cke are disabled during power-down. input buffers, excluding cke, ar e disabled during self-refresh. cs# input chip select: all commands are masked when cs# is registered high. cs# provides for external rank selection on systems with multiple ranks. cs# is considered part of the command code. odt input on die termination: odt (registered high) enab les termination resistance internal to the ddr3 sdram. when enabled, odt is only applied to each dq, dqs, dqs# and dm/tdqs, nu/tdqs# (when tdqs is enabled via mode register a11=1 in mr1) signal for x4/x8 configurations. for x16 configuration odt is applied to each dq, dqsu, dqsu#, dqsl, dqsl#, dmu, and dml signal. the odt pin will be ignored if mr1 is programmed to disable odt. ras#. cas#. we# input command inputs: ras#, cas# and we# (along with cs#) define the command being entered. dm, (dmu), (dml) input input data mask: dm is an input mask signal fo r write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. for x8 device, the function of dm or tdqs/tdqs# is enabled by mode register a11 setting in mr1. ba0 - ba2 input bank address inputs: ba0 - ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines if the mode register or extended mode register is to be accessed during a mrs cycle. a0 - a15 input address inputs: provide the row address for active commands and the column address for read/write commands to select one location ou t of the memory array in the respective bank. (a10/ap and a12/bc# have additional functions, see below). the address inputs also provide the op-c ode during mode register set commands. a10 / ap input auto-precharge: a10 is sampled during re ad/write commands to determine whether autoprecharge should be performed to the acce ssed bank after the read/write operation. (high: autoprecharge; low: no autoprecharge).a10 is sampled during a precharge command to determine whether the precharge a pplies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharg ed, the bank is selected by bank addresses. a12 / bc# input burst chop: a12 / bc# is sampled during read and write commands to determine if burst chop (on-the-fly) wi ll be performed. (high, no burst chop; low: burst choppe d). see command truth table for details. reset# input active low asynchronous reset: reset is active when reset# is low, and inactive when reset# is high. reset# must be high during normal operation. reset# is a cmos rail to rail signal with dc high and low at 80% and 20% of v dd , i.e. 1.20v for dc high and 0.30v for dc low. rev. 0.5 /sep 2007 9 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp dq input / output data input/ output: bi -directional data bus. dqu, dql, dqs, dqs#, dqsu, dqsu#, dqsl, dqsl# input / output data strobe: output with read data, input wi th write data. edge-aligned with read data, centered in write data. for the x16, dqsl co rresponds to the data on dql0-dql7; dqsu corresponds to the data on dqu0-dqu7. the da ta strobe dqs, dqsl, and dqsu are paired with differential signals dqs#, dqsl#, and dqsu#, respectively, to provide differential pair signaling to the system during reads and writes. ddr3 sdram supports differential data strobe only and does not support single-ended. tdqs, tdqs# output termination data strobe: tdqs/tdqs# is applicable for x8 drams only. when enabled via mode register a11 = 1 in mr1, the dram w ill enable the same termination resistance function on tdqs/tdqs# that is applied to dq s/dqs#. when disabled via mode register a11 = 0 in mr1, dm/tdqs will provide the data mask function and tdqs# is not used. x4/x16 drams must disable the tdqs function via mode register a11 = 0 in mr1. nc no connect: no internal elec trical connection is present. v ddq supply dq power supply: 1.5 v +/- 0.075 v v ssq supply dq ground v dd supply power supply: 1.5 v +/- 0.075 v v ss supply ground v refdq supply reference voltage for dq v refca supply reference voltage zq supply reference pin for zq calibration note: input only pins (ba0-ba2, a0-a15, ra s#, cas#, we#, cs#, cke, odt, dm, and reset#) do not supply termination. symbol type function rev. 0.5 /sep 2007 10 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 2. command description 2.1 command truth table (a) note 1,2,3,4 apply to the entire command truth table (b) note 5 applies to all read/write command [ba=bank address, ra=rank address, ca=column address, bc#=burst chop, x=don?t care, v=valid] function abbrevia tion cke cs# ras# cas# we# ba0- ba3 a13- a15 a12- bc# a10- ap a0- a9, a11 notes previous cycle current cycle mode register set mrs h h l l l l ba op code refresh ref h h l l l h v v v v v self refresh entry sre h l l l l h v v v v v 7,9,12 self refresh exit srx l h hv vv vvv vv 7,8,9,1 2 lh hh single bank precharge pre h h l l h l ba v v l v precharge all banks prea h h l l h l v v v h v bank activate act h h l l h h ba row address (ra) write (fixed bl8 or bc4) wr h h l h l l ba rfu v l ca write (bc4, on the fly) wrs4 h h l h l l ba rfu l l ca write (bl8, on the fly) wrs8 h h l h l l ba rfu h l ca write with auto precharge (fixed bl8 or bc4) wra h h l h l l ba rfu v h ca write with auto precharge (bc4, on the fly) wras4 h h l h l l ba rfu l h ca write with auto precharge (bl8, on the fly) wras8 h h l h l l ba rfu h h ca read (fixed bl8 or bc4) rd h h l h l h ba rfu v l ca read (bc4, on the fly) rds4 h h l h l h ba rfu l l ca read (bl8, on the fly) rds8 h h l h l h ba rfu h l ca read with auto precharge (fixed bl8 or bc4) rda h h l h l h ba rfu v h ca read with auto precharge (bc4, on the fly) rdas4 h h l h l h ba rfu l h ca read with auto precharge (bl8, on the fly) rdas8 h h l h l h ba rfu h h ca no operation nop h h l h h h v v v v v 10 device deselected des h h h x x x x x x x x 11 power down entry pde h l lh hh vvv vv6,12 hv vv power down exit pdx l h lh hh vvv vv6,12 hv vv rev. 0.5 /sep 2007 11 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp zq calibration long zqcl h h l h h l x x x h x zq calibration short zqcs h h l h h l x x x l x notes: 1. all ddr3 sdram commands are defined by states of cs #, ras#, cas#, we# and cke at the rising edge of the clock. the msb of ba, ra and ca are device density and configuration dependant. 2. reset# is low enable command which wi ll be used only for asynchronous reset so must be maintained high during any function. 3. bank addresses (ba) determine which bank is to be op erated upon. for (e)mrs ba selects an (extended) mode register. 4. ?v? means ?h or l (but a defined logic level)? and ?x? mean s either ?defined or undefine d (like floating) logic level?. 5. burst reads or writes cannot be terminated or inte rrupted and fixed/on the fly bl will be defined by mrs. 6. the power down mode does not perform any refresh operation. 7. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 8. self refresh exit is asynchronous. 9. vref(both vrefdq and vrefca) must be maintained during self refresh operation. 10. the no operation command should be used in cases when the ddr3 sdram is in an idle or wait state. the purpose of the no operation command (nop) is to preven t the ddr3 sdram from registering any unwanted commands between operations. a no operation command will not term inate a previous operation that is still executing, such as a burst read or write cycle. 11. the deselect command performs the sa me function as no operation command. 12. refer to the cke truth table for more detail with cke transition. function abbrevia tion cke cs# ras# cas# we# ba0- ba3 a13- a15 a12- bc# a10- ap a0- a9, a11 notes previous cycle current cycle rev. 0.5 /sep 2007 12 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 2.2 cke truth table a) notes 1-7 apply to th e entire cke truth table. b) cke low is allowed only if tmrd and tmod are satisfied. current state 2 cke command (n) 3 ras#, cas#, we#, cs# action (n) 3 notes previous cycle 1 (n-1) current cycle 1 (n) power-down l l x maintain power-down 14, 15 l h deselect or nop power-down exit 11,14 self-refresh l l x maintain self-refresh 15,16 l h deselect or nop self-refresh exit 8,12,16 bank(s) active h l deselect or nop a ctive power-down entry 11,13,14 reading h l deselect or nop power-down entry 11,13,14,17 writing h l deselect or nop pow er-down entry 11,13,14,17 precharging h l deselect or nop p ower-down entry 11,13,14,17 refreshing h l deselect or nop p recharge power-down entry 11 all banks idle h l deselect or nop precharge power-down entry 11,13,14,18 h l refresh self-refresh 9,13,18 for more details with all signals see ?2.1 command truth table? on page 10.. 10 notes: 1. cke (n) is the logic state of cke at clock edge n; ck e (n-1) was the state of cke at the previous clock edge. 2. current state is defined as the state of th e ddr3 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n), odt is not included here. 4. all states and sequences no t shown are illegal or reserved unless explic itly described elsewhere in this document. 5. the state of odt does not affect the states described in this table. the odt functi on is not available during self-refresh. 6. tckemin of [tbd] clocks means cke must be registered on [tbd] consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the [tbd] clocks of registration. thus, after any cke transition, cke may not transition from its vali d level during the time period of tis + [tbd] + tih. 7. deselect and nop are defined in the command truth table. 8. on self-refresh exit deselect or nop commands must be issued on every clock edge occurring during the txs period. read or odt commands may be issued only after txsdll is satisfied. 9. self-refresh mode can only be entered from the all banks idle state. 10. must be a legal command as defined in the command truth table. 11. valid commands for power-down entry and exit are nop and deselect only. 12. valid commands for self-refresh exit are nop and deselect only. 13. self-refresh can not be entered during read or wr ite operations. for a detailed list of restrictions see 8.2.1 on page 44 . 14. the power-down does not perform any refresh operations. 15. ?x? means ?don?t care? (including floating around vref) in self-refresh and power-down. it also applies to address pins. 16. vref (both vref_dq and vref_ca) must be maintained during self-refresh operation. 17. if all banks are closed at the conclusion of the read , write or precharge command, then precharge power-down is entered, otherwise active power-down is entered. 18. ?idle state? is defined as all banks are closed (trp, tdal, et c. satisfied), no data bursts are in progress, cke is high, and all timings from previous operatio ns are satisfied (tmrd, tmod, trfc, tzqinit, tzqoper, tzqcs, etc . ) as well as all self-refresh exit and power-down exit parameters are satisfied (txs, txp, txpdll, etc). rev. 0.5 /sep 2007 13 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 3. absolute maximum ratings symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.975 v v 3 vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.975 v v 3 vin, vout voltage on any pin relative to vss - 0.4 v ~ 1.975 v v tstg storage temperature -55 to +100 2 notes: 1. stresses greater than those listed under ?absolute maxi mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operatio n of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each other at all times;and vref must not be greater than 0.6xvddq,when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. rev. 0.5 /sep 2007 14 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 4. operating conditions 4.1 operating temperature condition 4.2 recommended dc operating conditions symbol parameter rating units notes toper operating temperature (tcase) 0 to 85 o c 2 extended temperature range 85 to 95 o c1,3 notes: 1. operating temperature toper is the case surface temperature on the center / top side of the dram. for measurement conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperatur es where all dram specifications will be supported. during operation, the dram case temperature must be maintained between 0 - 85oc under all operating conditions. 3. some applications require operation of the dr am in the extended temperature range between 85 o c and 95 o c case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9 s. (this double refresh requirement may not apply for so me devices.) it is also possible to specify a component with 1x refresh (trefi to 7.8s) in the extended te mperature range. please refer to supplier data sheet and/or the dimm spd for option availability. b) if self-refresh operation is required in the ex tended temperature range, then it is mandatory to either use the manual self-refresh mode with extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b) or enable the optional auto self-refresh mode (mr2 a6 = 1b and mr2 a7 = 0b). symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.500 1.575 v 1,2 vddq supply voltage for output 1.425 1.500 1.575 v 1,2 notes: 1. under all conditions, vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac paramaters are measured with vdd and vddq tied together. rev. 0.5 /sep 2007 15 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 5. ac and dc inpu t measurement levels 5.1 ac and dc logic input leve ls for single-ended signals the dc-tolerance limits and ac -noise limits for the refere nce voltages vrefca and vrefdq are illustrated in below figure. it shows a valid reference voltage vref(t) as a function of time. (vref stands for vrefca and vrefdq likewise). vref(dc) is the linear average of vref(t) over a very l ong period of time (e.g. 1 sec). this average has to meet the min/max requirements in table 1. furthermore vref(t) may temporarily deviate from vref(dc) by no more than +/- 1% vdd. illustration of vref(dc) tolerance and vref ac-noise limits single ended ac and dc input levels symbol parameter ddr3-800, ddr3-1066, ddr3-1333, ddr3-1600 unit notes min max vih(dc) dc input logic high vref + 0.100 tbd v 1 vil(dc) dc input logic low tbd vref - 0.100 v 1 vih(ac) ac input logic high vref + 0.175 - v 1, 2 vil(ac) ac input logic low vref - 0.175 v 1, 2 v refdq(dc) reference voltage for dq, dm inputs 0.49 * vdd 0.51 * vdd v 3, 4 v refca(dc) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd v 3, 4 vtt termination voltage for dq, dqs outputs vddq/2 - tbd vddq/2 + tbd notes: 1. for dq and dm, vref = vrefdq. for input any pins except reset#, vref = vrefca. 2. the ?t.b.d.? entries might change based on overshoot and undershoot specification. 3. the ac peak noise on v ref may not allow v ref to deviate from v ref(dc) by more than +/-1% vdd (for reference: approx. +/- 15 mv). 4. for reference: approx. vdd/2 +/- 15 mv. vdd vss vdd/2 v ref(dc) v ref ac-noise voltage time v ref(dc)max v ref(dc)min v ref (t) rev. 0.5 /sep 2007 16 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 5.2 ac and dc logic input leve ls for differential signals note1. refer to ?overshoot and undershoot specification on page 23? 5.3 differential inpu t cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (ck, ck# and dqs, dqs#) must meet the requirements below table. the differential input cross point voltage vi x is measured from the actual cross point of true and complement signal to the midlevel between of vdd and vss. vix definition cross point voltage for differ ential input signals (ck, dqs) symbol parameter ddr3-800, ddr3-1066, ddr3-1333, ddr3-1600 unit notes min max vihdiff differential inpu t logic high + 0.200 - v 1 vildiff differential input logic low - 0.200 v 1 symbol parameter ddr3-800, ddr3-1066, ddr3-1333, ddr3-1600 unit notes min max v ix differential input cross point voltage relative to vdd/2 - 150 150 mv vdd vss vdd/2 v ix v ix v ix ck#, dqs# ck, dqs rev. 0.5 /sep 2007 17 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 5.4 slew rate definitions fo r single ended input signals 5.4.1 input slew rate for input setup time (tis) and data setup time (tds) setup (tis and tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref and the first crossing of vih(ac)min. setup (tis and tds) nomi nal slew rate for a falling signal is defined as the slew rate between the last crossi ng of vref and the first crossing of vil(ac)max. 5.4.2 input slew rate for input hold time (tih) and data hold time (tdh) hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of vref. hold (tih and tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc )min and the first crossing of vref. single-ended input sl ew rate definition input nominal slew rate defi nition for single-ended signals description measured defined by applicable for min max input slew rate for rising edge vref vih(ac)min vih(ac)min-vref delta trs setup (tis, tds) input slew rate for falling edge vref vil(ac)max vref-vil(ac)max delta tfs input slew rate for rising edge vil(dc)max vref vref-vil(dc)max delta tfh hold (tih, tdh) input slew rate for falling edge vih(dc)min vref vih(dc)min-vref delta trh delta tfs delta trs vih(ac)m in vih (dc)m in vih (dc)m ax vih(ac)m ax vrefd q or vrefca part a: set up single ended input voltage(dq,add, cmd) part b: hold delta tfh delta trh vih (ac)m in vih (d c)m in vih (d c)m ax vih (ac)m ax vrefd q or vrefca single ended input voltage(dq,add, cmd) figure 82 ? in p u t n o m in a l s le w r a te d e fin itio n fo r s in g le -e n d e d s ig n a ls rev. 0.5 /sep 2007 18 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 5.5 slew rate definitions fo r differential input signals input slew rate for differential signals (ck, ck# and dqs, dqs#) are defined and measured as shown in table and figure . note: the differential signal (i.e. ck-ck and dqs-dqs ) must be linear between these thresholds. description measured defined by min max differential input slew rate for rising edge (ck-ck and dqs-dqs ) vildiffmax vihdiffmin vihdiffmin-vildiffmax deltatrdiff differential input slew rate for falling edge (ck-ck and dqs-dqs ) vihdiffmin vildiffmax vihdiffmin-vildiffmax deltatfdiff delta tfdiff delta trdiff vihdiffmin vildiffmax 0 differential input voltag e (i.e. dqs-dqs; ck-ck) differential input slew rate definition for dqs, dqs# and ck, ck# rev. 0.5 /sep 2007 19 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 6. ac and dc output measurement levels 6.1 single ended ac and dc output levels table shows the output levels used for measurements of single ended signals. 6.1.1 differential ac and dc output levels below table shows the output levels used for measurements of differential signals. 6.2 single ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between vol(ac) and vo h(ac) for single ended signals as shown in table and figure. note: output slew rate is verified by design and characte risation, and may not be subject to production test. symbol parameter ddr3-800, 1066, 1333 and 1600 unit notes voh(dc) dc output high measurement level (for iv curve linearity) 0.8 x vddq v vom(dc) dc output mid measurement level (for iv curve linearity) 0.5 x vddq v vol(dc) dc output low measurement le vel (for iv curve linearity) 0.2 x vddq v voh(ac) ac output high measurement level (for output sr) vtt + 0.1 x vddq v 1 vol(ac) ac output low measurement level (for output sr) vtt - 0.1 x vddq v 1 1. the swing of 0. 1 x vddq is based on approximately 50% of the stat ic single ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to vtt = vddq / 2. symbol parameter ddr3-800, 1066, 1333 and 1600 unit notes vohdiff(ac) ac differential output high measurement level (for output sr) + 0.2 x vddq v 1 voldiff(ac) ac differential output low meas urement level (for outtput sr) - 0.2 x vddq v 1 1. the swing of 0.2 x vddq is based on approximately 50% of the stat ic differential output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to vtt = vddq/2 at each of the differential outputs. description measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) voh(ac)-vol(ac) deltatrse single ended output slew rate for falling edge voh(ac) vol(ac) voh(ac)-vol(ac) deltatfse rev. 0.5 /sep 2007 20 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp fig. single ended output slew rate definition parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units min max min max min max min max single-ended output slew rate srqse 2.5 5 2.5 5 2.5 5 tbd 5 v/ns delta tfse delta trse voh(ac) vol(ac) v single ended output voltage(l.e.dq) single ended output slew rate definition table. output slew rate (single-ended) *** for ron = rzq/7 setting rev. 0.5 /sep 2007 21 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 6.3 differential output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between voldiff(ac) and vohdiff(ac) for di fferential signals as shown in table and figure . differential output slew rate definition note: output slew rate is verified by design and characte rization, and may not be subject to production test. fig. differential output slew rate definition table. differential output slew rate ***for ron = rzq/7 setting description measured defined by from to differential output slew rate for rising edge voldiff(ac) vohdiff(ac) vohdiff(ac)-voldiff(ac) deltatrdiff differential output slew rate for falling edge vohdiff(ac) voldiff(ac) vohdiff(ac)-voldiff(ac) deltatfdiff parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units min max min max min max min max differential output slew rate srqdiff 5 10 5 10 5 10 tbd 10 v/ns delta tfdiff delta trdiff vohdiff(ac) voldiff(ac) o differential output voltage(i.e. dqs-dqs) differential output slew rate definition rev. 0.5 /sep 2007 22 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 6.4 reference load for ac ti ming and output slew rate figure represents the effective reference load of 25 ohms used in defining the relevant ac timing parameters of the device as well as output slew rate measurements. it is not intended as a precise representation of any particul ar system environment or a depiction of the actual load pre- sented by a production tester. system desi gners should use ibis or ot her simulation tools to correlate the timing reference load to a system environment. manufactur ers correlate to their production test co nditions, generally one or more coaxial transmission lines terminated at the tester electronics. dut dq dqs dqs vddq 25 ohm vtt = vddq/2 ck, ck reference load for ac timing and output slew rate rev. 0.5 /sep 2007 23 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 7. overshoot and undershoot specifications 7.1 address and control overshoot and undershoot specifications table. ac overshoot/under shoot specification for address and control pins description specification ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 maximum peak amplitude allowed for overshoot area (see figure) 0.4v 0.4v 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure) 0.4v 0.4v 0.4v 0.4v maximum overshoot area above vdd (see figure) 0.67 v-ns 0.5 v-ns 0.4 v-ns 0.33 v-ns maximum undershoot area below vss (see figure) 0.67 v-ns 0.5 v-ns 0.4 v-ns 0.33 v-ns m axim um am plitude overshoot area vdd vss maximum amplitude undershoot area time (ns) address and control overshoot and undershoot definition rev. 0.5 /sep 2007 24 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 7.2 clock, data, strobe and mask overshoot and un dershoot specifications table. ac overshoot/undersh oot specification for clock, data, strobe and mask description specification ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 maximum peak amplitude allowed for overshoot area (see figure) 0.4v 0.4v 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure) 0.4v 0.4v 0.4v 0.4v maximum overshoot area above vddq (see figure) 0.25 v-ns 0.19 v-ns 0.15 v-ns 0.13 v-ns maximum undershoot area below vssq (see figure) 0.25 v-ns 0.19 v-ns 0.15 v-ns 0.13 v-ns m axim um am plitude overshoot area vddq vssq maximum amplitude undershoot area time (ns) clock, data strobe and mask overshoot and undershoot definition volts (v) rev. 0.5 /sep 2007 25 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 7.3 34 ohm output driver dc electrical characteristics a functional representation of the output buffer is show n in figure . output driver impedance ron is defined by the value of the external reference resistor rzq as follows: ron34 = rzq / 7 (nominal 34.3 w 10 % with nominal rzq = 240 w 1%) the individual pull-up and pull-down resistor s (ronpu and ronpd) are defined as follows: under the condition that ronpd is turned off under the condition that ronpu is turned off ron pu v ddq v out ? i out -------------------- ------------------ = ron pd v out i out -------------- - = to other circuitry like rcv, ... ipu ronpu ronpd ipd output driver iout vout vssq dq vddq chip in drive mode output driver: definition of voltages and currents rev. 0.5 /sep 2007 26 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp notes: 1. the tolerance limits are specified af ter calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. the tolerance limits are specified under the condition that vddq = vdd and that vssq = vss. 3. pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x vddq. other calibration schemes may be used to achieve the lineari ty spec shown above, e.g. calibration at 0.2 x vddq and 0.8 x vddq. 4. measurement definition for mismatch between pull-up and pull-down, mmpupd: measure ronpu and ronpd, both at 0.5 x vddq: 7.4 output driver temperature and voltage sensitivity if temperature and/or voltage change af ter calibration, the tolerance limits widen according to table and table . dt = t - t(@calibration); dv= vddq - vddq(@calibration); vdd = vddq drondt and drondv are not subject to production te st but are verified by design and characterization. output driver dc electrical characteristics, assuming r zq =240 ; entire operating temperature range; after proper zq calibration ron nom resistor v out min nom max unit notes 34 ron 34pd v oldc = 0.2 v ddq 0.6 1.0 1.1 r zq /7 1, 2, 3 v omdc = 0.5 v ddq 0.9 1.0 1.1 r zq /7 1, 2, 3 v ohdc = 0.8 v ddq 0.9 1.0 1.4 r zq /7 1, 2, 3 ron 34pu v oldc = 0.2 v ddq 0.9 1.0 1.4 r zq /7 1, 2, 3 v omdc = 0.5 v ddq 0.9 1.0 1.1 r zq /7 1, 2, 3 v ohdc = 0.8 v ddq 0.6 1.0 1.1 r zq /7 1, 2, 3 mismatch between pull-up and pull-down, mm pupd v omdc 0.5 v ddq -10 +10 % 1, 2, 4 output driver sensitivity definition min max unit ronpu@ v ohdc 0.6 - dr on dth*| t| - dr on dvh*| v| 1.1 + dr on dth*| t| + dr on dvh*| v| rzq/7 ron@ v omdc 0.9 - dr on dtm*| t| - dr on dvm*| v| 1.1 + dr on dtm*| t| + dr on dvm*| v| rzq/7 ronpd@ v oldc 0.6 - dr on dtl*| t| - dr on dvl*| v| 1.1 + dr on dtl*| t| + dr on dvl*| v| rzq/7 output driver voltage an d temperature sensitivity min max unit dr on dtm 0 1.5 %/ o c dr on dvm 0 0.15 %/mv dr on dtl 0 1.5 %/ o c dr on dvl 0 tbd %/mv mm pupd ron pu ron pd ? ron nom ---------------- ----------------- ---------------- x 100 = rev. 0.5 /sep 2007 27 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp these parameters may not be subject to production te st. they are verified by design and characterization. 7.5 on-die termination (odt) levels and i-v characteristics 7.5.1 on-die termination (odt) levels and i-v characteristics on-die termination effective resistance rtt is defined by bits a9, a6 and a2 of the mr1 register. odt is applied to the dq, dm, dqs/dqs# and tdqs/tdqs# (x8 devices only) pins. a functional representation of the on-die termination is sh own in figure . the individual pull-up and pull-down resistors (rttpu and rttpd) are defined as follows: under the condition that rttpd is turned off under the condition that rttpu is turned off dr on dth 01.5 %/ o c dr on dvh 0tbd%/mv output driver voltage an d temperature sensitivity min max unit rtt pu v ddq v out ? i out ------------------- -------------- = rtt pd v out i out ------------ - = to other circuitry like rcv, ... ipu rttpu rttpd ipd odt iout vout vssq dq vddq c h ip in t e rm in a tio n m o d e o n-d ie term ination : d efinition of voltages and currents iout = ipd-ipu io_ctt_definition_01 rev. 0.5 /sep 2007 28 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 7.5.2 odt dc electrical characteristics a below table provides an overview of the odt dc electrical characteristics. the values for rtt60pd120, rtt60pu120, rtt120pd240, rtt120pu240, rtt40pd80, rt t40pu80, rtt30pd60, rtt30pu60 , rt t20pd40, rtt20pu40 are not specifi- cation requirements, but can be used as design guide lines: odt dc electrical characteristics, assuming r zq =240 +/- 1% entire operating temperature range; after proper zq calibration mr1 a9, a6, a2 rtt resistor v out min nom max unit notes 0, 1, 0 120 rtt 120pd240 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq 1) 2) 3) 4) rtt 120pu240 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq 1) 2) 3) 4) rtt 120 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /2 1) 2) 5) 0, 0, 1 60 rtt 60pd120 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq /2 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /2 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq /2 1) 2) 3) 4) rtt 60pu120 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq /2 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /2 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq /2 1) 2) 3) 4) rtt 60 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /4 1) 2) 5) rev. 0.5 /sep 2007 29 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. the tolerance limits are specified under the condition that vddq = vdd and that vssq = vss. pull-down and pull-up odt resistors are recommended to be calibrated at 0.5 x vddq. other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x vddq and 0.8 x vddq. not a specification requiremen t, but a design guide line. measurement definition for rtt: 0, 1, 1 40 rtt 40pd80 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq /3 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /3 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq /3 1) 2) 3) 4) rtt 40pu80 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq /3 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /3 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq /3 1) 2) 3) 4) rtt 40 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /6 1) 2) 5) 1, 0, 1 30 rtt 30pd60 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq /4 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /4 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq /4 1) 2) 3) 4) rtt 30pu60 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq /4 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /4 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq /4 1) 2) 3) 4) rtt 30 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /8 1) 2) 5) 1, 0, 0 20 rtt 20pd40 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq /6 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /6 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq /6 1) 2) 3) 4) rtt 20pu40 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq /6 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /6 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq /6 1) 2) 3) 4) rtt 20 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /12 1) 2) 5) deviation of v m w.r.t. v ddq /2, d v m -5 +5 % 1) 2) 5) 6) odt dc electrical characteristics, assuming r zq =240 +/- 1% entire operating temperature range; after proper zq calibration mr1 a9, a6, a2 rtt resistor v out min nom max unit notes rev. 0.5 /sep 2007 30 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp apply vih(ac) to pin under test and measure current i(vih(ac)), then apply vil(ac) to pin un der test and measure current i(vil(ac)) respectively. measurement definition for vm and dvm : measure voltage (vm) at test pin (midpoint) with no load: 7.5.3 odt temperature and voltage sensitivity if temperature and/or voltage change after calibration, the tolerance limits widen according to table and table . dt = t - t(@calibration); dv= vddq - vddq(@calibration); vdd = vddq these parameters may not be subject to production te st. they are verified by design and characterization odt sensitivity definition min max unit rtt 0.9 - dr tt dt*| t| - dr tt dv*| v| 1.6 + dr tt dt*| t| + dr tt dv*| v| rzq/2,4,6,8,12 odt voltage and temperature sensitivity min max unit dr tt dt 0 1.5 %/ o c dr tt dv 0 0.15 %/mv rtt v ih(ac) v il(ac) ? i (vih(ac)) i (vil(ac)) ? ---------------------------------- ----------------------- = v m 2 v m ? v ddq ----------------- -1 ? ?? ?? 100 ? = rev. 0.5 /sep 2007 31 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 7.6 odt timing definitions 7.6.1 test load for odt timings different than for timing measurements, the refere nce load for odt timings is defined in figure . 7.6.2 odt timing reference load odt timing definitions definitions for taon, taonpd, taof, taofpd and tadc are pr ovided in the table and subs equent figures. measurement reference settings are provided in the table. odt timing definitions symbol begin point definition end point definition figure t aon rising edge of ck - ck# defined by the end point of odtlon extrapolated po int at vssq figure t aonpd rising edge of ck - ck# with odt being first registered high extrapolated po int at vssq figure t aof rising edge of ck - ck# defined by the end point of odtloff end point: extrapolated point at vrtt_nom figure t aofpd rising edge of ck - ck# with odt being first registered low end point: extrapolated point at vrtt_nom figure t adc rising edge of ck - ck# defined by the end point of odtlcnw, odtlcwn4 or odtlcwn8 end point: extrapolated point at vrtt_wr and vrtt_nom respectively figure reference settings for odt timing measurements measured parameter rtt_nom setting rtt_wr setting v sw1 [v] v sw2 [v] note t aon r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aonpd r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aof r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aofpd r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t adc r zq /12 r zq /2 0.20 0.30 bd_refload_odt ck ck, vddq dqs dqs, tdqs tdqs, dq, dm dut vtt = vssq rtt = 25 vssq timing reference points rev. 0.5 /sep 2007 32 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp definition of taon definition of taonpd ck ck vtt td_taon_def t aon vssq dqs dq, dm vssq dqs, tdqs tdqs, begin point: rising edge of ck - ck defined by the end point of odtlon v sw1 v sw2 end point: extrapolated point at vssq t sw1 t sw2 ck ck vtt td_taonpd_def t aonpd vssq dqs dq, dm vssq dqs, tdqs tdqs, begin point: rising edge of ck - ck with odt being first registered high v sw1 v sw2 end point: extrapolated point at vssq t sw1 t sw2 rev. 0.5 /sep 2007 33 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp definition of taof definition of taofpd ck ck vtt td_taof_def t aof dqs dq, dm dqs, tdqs tdqs, begin point: rising edge of ck - ck defined by the end point of odtloff end point: extrapolated point at vrtt_nom vrtt_nom vssq v sw1 v sw2 t sw1 t sw2 ck ck vtt td_taofpd_def t aofpd dqs dq, dm dqs, tdqs tdqs, begin point: rising edge of ck - ck with odt being first registered low end point: extrapolated point at vrtt_nom vrtt_nom vssq v sw1 v sw2 t sw1 t sw2 rev. 0.5 /sep 2007 34 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp definition of tadc 8. idd specification parameters and test conditions 8.1 idd measurement conditions within the tables provided further down , an overview about the idd measuremen t conditions is provided as follows: within the tables about idd measurement cond itions, the following definitions are used: low is defined as vin <= vilac(max.); high is defin ed as vin >= vihac(min.). stable is defined as inputs are stable at a high or low level. floating is defined as inputs are vref = vddq / 2. switching is defined as described in the following 2 tables. overview of tables providing idd meas urement conditions and dram behavior table number measurement conditions table on page 36 idd0 and idd1 table on page 37 idd2n, id d2q, idd2p(0), idd2p(1) table on page 38 idd3n and idd3p table on page 38 idd4r, idd4w, idd7 table on page 40 idd7 for different speed grades and different trrd, tfaw conditions table on page 40 idd5b table on page 41 idd6, idd6et (optional), idd6tc (optional) ck ck td_tadc_def t adc dqs dq, dm dqs, tdqs tdqs, v sw1 v sw2 end point: extrapolated point at vrtt_nom t sw11 t sw21 t adc end point: extrapolated point at vrtt_wr vtt vssq vrtt_nom vrtt_wr vrtt_nom t sw12 t sw22 begin point: rising edge of ck - ck defined by the end point of odtlcnw begin point: rising edge of ck - ck defined by the end point of odtlcwn4 or odtlcwn8 rev. 0.5 /sep 2007 35 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp timing parameters are listed in the following table: definition of switching for ad dress and command input signals switching for address (row, column) and command signals (cs , ras , cas , we ) is defined as: address (row, column) if not otherwise mentioned the inputs are stab le at high or low during 4 clocks and change then to the opposite value (e.g. ax ax ax ax ax ax ax ax ax ax ax ax ..... please see each iddx definition for details bank address if not otherwise mentioned the bank addresse s should be switched like the row/column addresses - please see each iddx definition for details command (cs , ras , cas , we ) define d = {cs , ras , cas , we } = {high, low, low, low} define d = {cs , ras , cas , we } = {high, high,high,high} define command background pattern = d d d d d d d d d d d d ... if other commands are necessary (e.g. act for idd0 or read for idd4r), the background pattern command is substituted by the respective cs , ras , cas , we levels of the necessary command. see each iddx definition for detai ls and figures 1,2,3 as examples. definition of switching for data (dq) switching for data (dq) is defined as data (dq) data dq is changing between high and low every other data transfer (once per clock) for dq signals, which means that data dq is stab le during one clock; see each iddx definition for exceptions from this ru le and for further details. see figures 1,2,3 as examples. data masking (dm) no switching; dm must be driven low all the time for idd testing the followin g parameters are utilized. parameter bin ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit 5-5-5 6-6-6 6-6-6 7-7-7 8-8-8 7-7-7 8-8-8 9-9-9 8-8-8 9-9-9 101010 t ckmin (idd) 2.5 1.875 1.5 1.25 ns cl(idd) 5 6 6 7 8 7 8 9 8 9 10 t rcdmin (idd) 12.5 15 11.25 13.13 15 1 0.5 12 13.5 10 11.25 12.5 ns t rcmin (idd) 50 52.5 48.75 50.63 52.50 46.5 48 49.5 tbd tbd tbd ns t rasmin (idd) 37.5 37.5 37.5 37.5 37.5 36 36 36 tbd tbd tbd ns t rpmin (idd) 12.5 15 11.25 13.13 15 1 0.5 12 13.5 10 11.25 12.5 ns t faw (idd) x4/x8 40 40 37.5 37.5 37.5 30 30 30 30 30 30 ns x16505050505045454540 40 40ns t rrd (idd) x4/x8 10 10 7.5 7.5 7.5 6.0 6.0 6.0 6.0 6.0 6.0 ns x16 10 10 10 10 10 7.5 7.5 7.5 7.5 7.5 7.5 ns t rfc (idd) -512mb 90 90 90 90 90 90 90 90 90 90 90 ns t rfc (idd) -1 gb 110 110 110 110 110 110 110 110 110 110 110 ns t rfc (idd) - 2 gb 160 160 160 160 160 160 160 160 160 160 160 ns t rfc (idd) - 4 gb tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns rev. 0.5 /sep 2007 36 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp t he following conditions apply: idd specifications are tested after the device is properly initialized. input slew rate is specified by ac parametric test conditions. idd parameters are specified with odt and output buffer disabled (mr1 bit a12). idd measurement conditions for idd0 and idd1 current i dd0 i dd1 name operating current 0 -> one bank activate -> precharge operating current 1 -> one bank activate -> read -> precharge measurement condition timing diagram example figure 1 cke high high external clock on on t ck t ckmin (idd) t ckmin (idd) t rc t rcmin (idd) t rcmin (idd) t ras t rasmin (idd) t rasmin (idd) t rcd n.a. t rcdmin (idd) t rrd n.a. n.a. cl n.a. cl(idd) al n.a. 0 cs high between. activate and precharge commands high between activate, read and precharge command inputs (cs ,ras , cas , we ) switching as described in table only exceptions are activate and precharge commands; example of idd0 pattern: a0 ddd dddd dddd ddd p0 (ddr3-800: t ras = 37.5ns between (a)ctivate and (p)recharge to bank 0; definition of d and d : see rev. 0.5 /sep 2007 37 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp idle banks all other all other precharge power down mode / mode register bit 12 n.a. n.a. idd measurement conditions for idd2 n, idd2p(1), idd2p(0) and idd2q current i dd2n i dd2p (1) a a. i dd2p (0) i dd2q name precharge standby current precharge power down current fast exit - mrs a12 bit = 1 precharge power down current slow exit - mrs a12 bit = 0 precharge quiet standby current measurement condition timing diagram example figure cke high low low high external clock on on on on t ck t ckmin (idd) t ckmin (idd) t ckmin (idd) t ckmin (idd) t rc n.a. n.a. n.a. n.a. t ras n.a. n.a. n.a. n.a. t rcd n.a. n.a. n.a. n.a. t rrd n.a. n.a. n.a. n.a. cl n.a. n.a. n.a. n.a. al n.a. n.a. n.a. n.a. cs high stable stable high bank address, row addr. and command inputs switching as described in table stable stable stable data inputs switching fl oating floating floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] disabled / [0,0] disabled / [0,0] burst length n.a. n.a. n.a. n.a. active banks none none none none idle banks all all all all precharge power down mode / mode register bit a n.a. fast exit / 1 (any valid command after txp b ) b. slow exit / 0 slow exit (rd and odt commands must satisfy txpdll-al) n.a. idd measurement conditions for idd0 and idd1 current i dd0 i dd1 name operating current 0 -> one bank activate -> precharge operating current 1 -> one bank activate -> read -> precharge a. in ddr3, the mrs bit 12 defines dll on/off behaviour only for precharge power down. there are 2 different precharge power down state possible: one with dll on(f ast exit, bit 12=1) and one with dll off(slow exit, bit 12=0). b. because it is an exit after precharge power down, th e valid commands are: activate, refresh mode-register set, enter-self refresh. rev. 0.5 /sep 2007 38 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp idd measurement conditions fo r idd3n and idd3p(fast exit) current i dd3n i dd3p name active standby current active power-down current a always fast exit measurement condition timing diagram example figure cke high low external clock on on t ck t ckmin (idd) t ckmin (idd) t rc n.a. n.a. t ras n.a. n.a. t rcd n.a. n.a. t rrd n.a. n.a. cl n.a. n.a. al n.a. n.a. cs high stable addr. and cmd inputs switching as described in table stable data inputs switching as described in table floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] burst length n.a. n.a. active banks all all idle banks none none precharge power down mode / mode register bit a n.a. n.a.(active power down mode is always ?fast exit? with dll on) a.ddr3 will offer only one active power down mode with dll on (-> fast exit). mrs bit 12 will not be used for active power down. instead bit 12 will be used to switch betw een two different precharge power down modes. idd measurement conditions for idd4r, idd4w and idd7 current i dd4r i dd4w i dd7 name operating current burst read operating current burst write all bank interleave read current measurement condition timing diagram example rev. 0.5 /sep 2007 39 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp cs high btw. valid cmds high btw. valid cmds high btw. valid cmds command inputs (cs , ras , cas , we ) switching as described in table; exceptions are read commands => idd4r pattern: r0 ddd r1 ddd r2 ddd r3 .ddd r4 ..... rx = read from bank x; definition of d and d : see table switching as described in table; exceptions are write commands => idd4w pattern: w0 ddd w1 ddd w2 ddd w3 ddd w4 ... wx = write to bank x; definition of d and d : see table for patterns see table row, column addresses column addresses switching as described in table; address input a10 must be low all the time! column addresses switching as described in table; address input a10 must be low all the time! stable during deselects bank addresses bank address cycling (0 -> 1 -> 2 -> 3 ...) bank address cycling (0 -> 1 -> 2 -> 3 ...) bank address cycling (0 -> 1 -> 2 -> 3 ...), see pattern in table dq i/o seamless read data burst (bl8): output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to ?1?. seamless write data burst (bl8): input data switches every clock, which means that write data is stable during one clock cycle. dm is low all the time. read data (bl8): output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to ?1?. output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] disabled / [0,0] burst length 8 fixed / mr0 bits [a1, a0] = {0,0} 8 fixed / mr0 bits [a1, a0] = {0,0} 8 fixed / mr0 bits [a1, a0] = {0,0} active banks all all all, rotational idle banks none none none precharge power down mode / mode register bit n.a. n.a. n.a. idd measurement conditions for idd4r, idd4w and idd7 current i dd4r i dd4w i dd7 name operating current burst read operating current burst write all bank interleave read current rev. 0.5 /sep 2007 40 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp idd7 pattern for different speed grades and different trrd, tfaw conditions speed bin org. tfaw tfaw trrd trrd idd7 pattern a a.a0 = activation of bank 0; ra0 = read wi th auto-precharge of bank 0; d = deselect mb/s [ns] [clk] [ns] [clk] (note this entire sequence is repeated.) 800 all x4/x8 40 16 10 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d all x16 50 20 10 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d 1066 all x4/x8 37.5 20 7.5 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d all x16 50 27 10 6 a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d d d d a3 ra3 d d d d d d d a4 ra4 d d d d a5 ra5 d d d d a6 ra6 d d d d a7 ra7 d d d d d d d 1333 all x4/x8 30 20 6 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d all x16 45 30 7.5 5 a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3 ra3 d d d d d d d d d d d d d a4 ra4 d d d a5 ra5 d d d a6 ra6 d d d a7 ra7 d d d d d d d d d d d d d 1600 all x4/x8 30 24 6 5 a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3 ra3 d d d d d d d a4 ra4 d d d a5 ra5 d d d a6 ra6 d d d a7 ra7 d d d d d d d all x16 40 32 7.5 6 a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d d d d a3 ra3 d d d d d d d d d d d d a4 ra4 d d d d a5 ra5 d d d d a6 ra6 d d d d a7 ra7 d d d d d d d d d d d d idd measurement conditions for idd5b current i dd5b name burst refresh current measurement condition cke high external clock on t ck t ckmin (idd) t rc n.a. t ras n.a. t rcd n.a. t rrd n.a. t rfc t rfcmin (idd) cl n.a. al n.a. cs high btw. valid cmds addr. and cmd inputs switching data inputs switching output buffer dq,dqs / mr1 bit a12 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] rev. 0.5 /sep 2007 41 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp burst length n.a. active banks refresh command every trfc=trfcmin idle banks none precharge power down mode / mode register bit n.a. idd measurement conditions for idd6, idd6et, and idd6tc current i dd6 i dd6et ( optional) i dd6tc (optional) name self-refresh current normal temperature range t case = 0 .. 85 self-refresh current extended temperature range a t case = 0 .. 95 auto self refresh current tcase-see table measurement condition temperature t case = 85 t case = 95 tcase-see table auto self refresh (asr) / mr2 bit a6 disabled / ?0? disalbed / ?0? enabled / ?1? self refresh temperature range (srt) / mr2 bit a7 normal / ?0? extended / ?1? disabled / ?0? cke low low low external clock off; ck and ck at low off; ck and ck at low off; ck and ck at low t ck n.a. n.a. n.a. t rc n.a. n.a. n.a. t ras n.a. n.a. n.a. t rcd n.a. n.a. n.a. t rrd n.a. n.a. n.a. cl n.a. n.a. n.a. al n.a. n.a. n.a. cs floating floating floating command inputs (ras , cas , we ) floating floating floating row, colum addresses floating floating floating bank addresses floating floating floating data i/o floating floating floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] disabled / [0,0] burst length n.a. n.a. n.a. active banks all during self-refresh actions all during self-refresh actions all during self-refresh actions idd measurement conditions for idd5b current i dd5b name burst refresh current rev. 0.5 /sep 2007 42 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp idle banks all btw. self-refresh ac tions all btw. self-refresh actions all btw. self-refresh actions precharge power down mode / mr0 bit a12 n.a. n.a. n.a. a. idd measurement conditions for idd6, idd6et, and idd6tc current i dd6 i dd6et ( optional) i dd6tc (optional) name self-refresh current normal temperature range t case = 0 .. 85 self-refresh current extended temperature range a t case = 0 .. 95 auto self refresh current tcase-see table a. users should refer to the dram suppl ier data sheet and/or the dimm spd to determine if ddr3 sdram devices support the following options or requirem ents referred to in this material. rev. 0.5 /sep 2007 43 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 8.2 idd specifications idd values are for full operating range of voltage and temperature unless otherwise noted. i dd specification speed grade bin ddr3 - 800 5-5-5 ddr3 - 1066 7-7-7 ddr3 - 1333 8-8-8 ddr3 - 1600 9-9-9 unit notes symbol max. max. max. max. i dd0 tbd tbd tbd tbd ma x4/x8 tbd tbd tbd tbd ma x16 i dd1 tbd tbd tbd tbd ma x4/x8 tbd tbd tbd tbd ma x16 i dd2p (0) slow exit tbd tbd tbd tbd ma x4/x8/x16 i dd2p (1) fast exit tbd tbd tbd tbd ma x4/x8/x16 i dd2n tbd tbd tbd tbd ma x4/x8/x16 i dd2q tbd tbd tbd tbd ma x4/x8/x16 i dd3p (fast exit) tbd tbd tbd tbd ma x4/x8/x16 i dd3n tbd tbd tbd tbd ma x4/x8/x16 i dd4r tbd tbd tbd tbd ma x4 tbd tbd tbd tbd ma x8 tbd tbd tbd tbd ma x16 i dd4w tbd tbd tbd tbd ma x4 tbd tbd tbd tbd ma x8 tbd tbd tbd tbd ma x16 i dd5b tbd tbd tbd tbd ma x4/x8/x16 i dd6 tbd tbd tbd tbd ma x4/x8 tbd tbd tbd tbd ma x16 i dd6et tbd tbd tbd tbd ma x4/x8 tbd tbd tbd tbd ma x16 i dd7 tbd tbd tbd tbd ma x4/x8 tbd tbd tbd tbd ma x16 rev. 0.5 /sep 2007 44 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 8.2.1 idd6 current definition 8.2.2 idd6tc specification (see notes 1~2) symbol parameter/condition i dd6 normal temperature range self-refresh current: cke 0.2v; external clock off, ck and ck# at 0v; other control and address inputs are floating; da ta bus inputs are fl oating, pasr disabled. applicable for mr2 settings a6 = 0 and a7 = 0. i dd6et extended temperature range self-refresh current: cke 0.2v; external clock off, ck and ck# at 0v; other control and address inputs are floating; da ta bus inputs are fl oating, pasr disabled. applicable for mr2 settings a6 = 0 and a7 = 1. i dd6tc auto self-refre sh current: cke 0.2v; external clock off, ck and ck# at 0v; other control and address inputs are floating; data bus inputs are floating, pasr disabled. ap plicable when asr is enabled by mr2 settings a6 = 1 and a7 = 0. symbol temperature range value unit notes i dd6 0 - 85 o c ma 3,4 i dd6et 0 - 95 o c ma 5,6 i dd6tc 0 o c ~ t a ma 6,7,8 t b ~ t y ma 6,7,8 t z ~ t opermax ma 6,7,8 1. some idd currents are higher for x16 organization due to larger page size architecture. 2. max. values for idd currents cons idering worst case conditions of process, temperature and voltage. 3. applicable for mr2 settings a6=0 and a7=0. 4. supplier data sheets include a max value for idd6. 5. applicable for mr2 settings a6=0 and a7=1. idd6et is only specified for devices which support the extended temperature range feature. 6. refer to the supplier data sheet for the value specific ation method (e.g. max, typical) for idd6et and idd6tc 7. applicable for mr2 settings a6=1 and a7=0. idd6tc is only specified for devices which su pport the auto self refresh feature. 8. the number of discrete temperature ranges supported and th e associated ta - tz values are supplier/design specific. temperature ranges are specified for all supported values of toper. refer to supplier data sheet for more information. rev. 0.5 /sep 2007 45 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 9. input/output capacitance ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 parameter symbol min max min max min max min max units notes input/output capacitance (dq, dm, dqs, dqs#, tdqs, tdqs#) c io 1.5 3.0 1.5 3.0 1.5 2.5 tbd tbd pf 1,2,3 input capacitance, ck and ck# c ck 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 pf 2,3 input capacitance delta ck and ck# c dck 0 0.15 0 0.15 0 0.15 0 0.15 pf 2,3,4 input capacitance (all other input-only pins) c i 0.75 1.5 0.75 1.5 0.75 1.3 0.75 1.3 pf 2,3,6 input capacitance delta, dqs and dqs# c ddqs 0 0.20 0 0.20 0 0.15 0 0.15 pf 2,3,5 input capacitance delta (all ctrl input-only pins) c di_ctrl -0.5 0.3 -0.5 0.3 -0.4 0. 2 -0.4 0.2 pf 2,3,7,8 input capacitance delta (all add/cmd input-only pins) c di_add_ cmd -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 pf 2,3,9,10 input/output capacitance delta (dq, dm, dqs, dqs#) c dio -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pf 2,3,11 notes: 1. although the dm, tdqs and tdqs# pins have di fferent functions, the loading matches dq and dqs. 2. this parameter is not subject to prod uction test. it is verified by design and characterization. the capacitance is measured according to jep147(?procedure for measuring input capacitance using a vector network analyzer(vna)?) with vdd, vddq, vss,vssq applied an d all other pins floating (except the pin under test, cke, reset# and odt as necessary). vdd=vddq=1.5v, vbias=vdd/2 and on-die termination off. 3. this parameter applies to mono lithic devices only; stacked/dual-die devices are not covered here 4. absolute value of c ck -c ck #. 5. the minimum c ck will be equal to the minimum c i . 6. input only pins include: odt, cs, cke, a0-a15, ba0-ba2, ras#, cas#, we#. 7. ctrl pins defined as odt, cs and cke. 8. c di_ctrl =c i (cntl) - 0.5 * c i (clk) + c i (clk#)) 9. add pins defined as a0-a15, ba0-ba2 and cmd pins are defined as ras#, cas# and we#. 10. c di_add_cmd =c i (add_cmd) - 0.5*(c i (clk)+c i (clk#)) 11. c dio =c io (dq) - 0.5*(c io (dqs)+c io (dqs#)) rev. 0.5 /sep 2007 46 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 10. standard speed bins ddr3 sdram standard speed bins include tck, trcd, trp, tras and trc for each corresponding bin. ddr3-800 speed bins for specific notes see ?speed bin table notes? on page 50.. speed bin ddr3-800d ddr3-800e unit notes cl - nrcd - nrp 5-5-5 6-6-6 parameter symbol min max min max internal read command to first data t aa 12.5 20 15 20 ns act to internal read or write delay time t rcd 12.5 ? 15 ? ns pre command period t rp 12.5 ? 15 ? ns act to act or ref command period t rc 50 ? 52.5 ? ns act to pre command period t ras 37.5 9 * trefi 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 2.5 3.3 reserved ns 1)2)3)4) cl = 6 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 ns 1)2)3) supported cl settings 5, 6 6 n ck supported cwl settings 55 n ck rev. 0.5 /sep 2007 47 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp ddr3-1066 speed bins for specific notes see ?speed bin table notes? on page 50. speed bin ddr3-1066e ddr3-1066f ddr3-1066g unit note cl - nrcd - nrp 6-6-6 7-7-7 8-8-8 parameter symbol min max min max min max internal read command to first data t aa 11.25 20 13.125 20 15 20 ns act to internal read or write delay time t rcd 11.25 ? 13.125 ? 15 ? ns pre command period t rp 11.25 ? 13.125 ? 15 ? ns act to act or ref command period t rc 48.75 ? 50.625 ? 52.5 ? ns act to pre command period t ras 37.5 9 * trefi 37.5 9 * trefi 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 2.5 3.3 reserved reserved ns 1)2)3)4)6) cwl = 6 t ck(avg) reserved reserved reserved ns 4) cl = 6 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 2.5 3.3 ns 1)2)3)6) cwl = 6 t ck(avg) 1.875 < 2.5 reserved reserved ns 1)2)3)4) cl = 7 cwl = 5 t ck(avg) reserved reserved reserved ns 4) cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 reserved ns 1)2)3)4) cl = 8 cwl = 5 t ck(avg) reserved reserved reserved ns 4) cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns 1)2)3) supported cl settings 5, 6, 7, 8 6, 7, 8 6, 8 n ck supported cwl settings 5, 6 5, 6 5, 6 n ck rev. 0.5 /sep 2007 48 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp ddr3-1333 speed bins for specific notes see ?speed bin table notes? on page 50.. speed bin ddr3-1333f (optional) ddr3-1333g ddr3-1333h ddr3-1333j (optional) unit note cl - nrcd - nrp 7-7-7 8-8-8 9-9-9 10-10-10 parameter symbol min max min max min max min max internal read command to first data t aa 10.5 20 12 20 13.5 20 15 20 ns act to internal read or write delay time t rcd 10.5 ? 12 ? 13.5 ? 15 ? ns pre command period t rp 10.5 ? 12 ? 13.5 ? 15 ? ns act to act or ref command period t rc 46.5 ? 48 ? 49.5 ? 51 ? ns act to pre command period t ras 36 9 * trefi 36 9 * trefi 36 9 * trefi 36 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 reserved reserved ns 1,2,3,4,7 cwl = 6, 7 t ck(avg) reserved reserved reserved reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns 1,2,3,7 cwl = 6 t ck(avg) 1.875 < 2.5 reserved reserved reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved reserved reserved reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 reserved reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) 1.5 <1.875 reserved reserved reserved ns 1,2,3,4 cl = 8 cwl = 5 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns 1,2,3,7 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 reserved reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 1.5 <1.875 reserved ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 1.5 <1.875 1.5 <1.875 ns 1,2,3 (optional) (optional) (optional) ns 5 supported cl settings 5, 6, 7, 8, 9 5, 6, 7, 8, 9 6, 8, 9 6, 8, 10 n ck supported cwl settings 5, 6, 7 5, 6, 7 5, 6, 7 5, 6, 7 n ck rev. 0.5 /sep 2007 49 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp ddr3-1600 speed bins for specific notes see ?speed bin table notes? on page 50.. speed bin ddr3-1600g (optional) ddr3-1600h ddr3-1600j ddr3-1600k (optional) unit note cl - nrcd - nrp 8-8-8 9-9-9 10-10-10 11-11-11 parameter symbol min max min max min max min max internal read command to first data t aa 10 20 11.25 20 12.5 20 13.75 20 ns act to internal read or write delay time t rcd 10 ? 11.25 ? 12.5 ? 13.75 ? ns pre command period t rp 10 ? 11.25 ? 12.5 ? 13.75 ? ns act to act or ref command period t rc 45 ? 46.25 ? 47.5 ? 48.75 ? ns act to pre command period t ras 35 9 * trefi 35 9 * trefi 35 9 * trefi 35 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 2.5 3.3 re served ns 1,2,3,4,8 cwl = 6, 7, 8 t ck(avg) reserved reserved reserved reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns 1,2,3,8 cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 reserved reserved ns 1,2,3,4,8 cwl = 7, 8 t ck(avg) reserved reserved reserved reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 reserved ns 1,2,3,4,8 cwl = 7 t ck(avg) 1.5 <1.875 reserved reserved reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved reserved reserved reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns 1,2,3,8 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 reserv ed reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) 1.25 < 1.5 reserved reserved reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 1.5 <1. 875 reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) 1.25 < 1.5 1.25 < 1.5 reserved reserved ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 1.5 <1.875 1.5 <1.875 ns 1,2,3,8 cwl = 8 t ck(avg) 1.25 < 1.5 1.25 < 1.5 1.25 < 1.5 reserved ns 1,2,3,4 cl = 11 cwl = 5, 6, 7 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 8 t ck(avg) 1.25 < 1.5 1.25 < 1.5 1.25 < 1.5 1.25 < 1.5 ns 1,2,3 (optional) (optional) (optional) ns 5 supported cl settings 5, 6, 7, 8, 9, 10 5, 6, 7, 8, 9, 10 5, 6, 7, 8, 9, 10 6, 8, 10, 11 n ck supported cwl settings 5, 6, 7, 8 5 , 6, 7, 8 5, 6, 7, 8 5, 6, 7, 8 n ck rev. 0.5 /sep 2007 50 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp speed bin table notes absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); notes: 1. the cl setting and cwl sett ing result in tck(avg).min and tck(avg).max requirements. when ma king a selection of tck(avg), both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 2. tck(avg).min limits: since cas latency is not purely analog - data and strobe output are synchronized by the dll - all possible intermediate frequencies may not be guaranteed . an application should use the next smaller jedec standard tck(avg) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating cl [nck] = taa [n s] / tck(avg) [ns], rounding up to the next ?supported cl?. 3. tck(avg).max limits: calculate tck(avg) = taa.max / clse lected and round the resulting tck(avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to clselected. 4. ?reserved? settings are not allowed. user must program a different value. 5. ?optional? settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. refer to supplier?s data sheet and spd in formation if and how this setting is supported. 6. any ddr3-1066 speed bin also supports functional operatio n at lower frequencies as shown in the table which are not subject to production tests bu t verified by design/characterization. 7. any ddr3-1333 speed bin also supports functional operatio n at lower frequencies as shown in the table which are not subject to production tests bu t verified by design/characterization. 8. any ddr3-1600 speed bin also supports functional operatio n at lower frequencies as shown in the table which are not subject to production tests bu t verified by design/characterization. 11. electrical characte ristics and ac timing timing parameters by speed bin note: the following general notes from page 57 apply to table : a ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 parameter symbol min max min max min max min max units notes clock timing minimum clock cycle time (dll off mode) tck (dll_off) 8- 8 - 8 - 8 -ns6 average clock period tck(avg) see ?10. standard speed bins? on page 46. ps f average high pulse width tch(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tck (avg) f average low pulse width tcl(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tck (avg) f absolute clock period tck (abs) tck (avg) min + tjit (per) min tck (avg) max + tjit (per) max tck (avg) min + tjit (per) min tck (avg) max + tjit (per) max tck (avg) min + tjit (per) min tck (avg) max + tjit (per) max tck (avg) min + tjit (per) min tck (avg) max + tjit (per) max ps absolute clock high pulse width tch (abs) 0.43 - 0.43 - 0.43 - 0.43 - tck (avg) 25 absolute clock low pulse width tcl(abs) 0.43 - 0.43 - 0.43 - 0.43 - tck (avg) 26 clock period jitter jit(per) - 100 100 - 90 90 - 80 80 - 70 70 ps rev. 0.5 /sep 2007 51 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp clock period jitter during dll locking period tjit (per, lck) - 90 90 - 80 80 - 70 70 -60 60 ps cycle to cycle period jitter tjit(cc) 200 180 160 140 ps cycle to cycle period jitter during dll locking period tjit (cc, lck) 180 160 140 120 ps duty cycle jitter tjit (duty) -- - - - - - -ps cumulative error across 2 cycles terr (2per) -147 147 -132 132 -118 118 -103 103 ps cumulative error across 3 cycles terr (3per) -175 175 -157 157 -140 140 -122 122 ps cumulative error across 4 cycles terr (4per) -194 194 -175 175 -155 155 -136 136 ps cumulative error across 5 cycles terr (5per) -209 209 -188 188 -168 168 -147 147 ps cumulative error across 6 cycles terr (6per) -222 222 -200 200 -177 177 -155 155 ps cumulative error across 7 cycles terr (7per) -232 232 -209 209 -186 186 -163 163 ps cumulative error across 8 cycles terr (8per) -241 241 -217 217 -193 193 -169 169 ps cumulative error across 9 cycles terr (9per) -249 249 -224 224 -200 200 -175 175 ps cumulative error across 10 cycles terr (10per) -257 257 -231 231 -205 205 -180 180 ps cumulative error across 11 cycles terr (11per) -263 263 -237 237 -210 210 -184 184 ps cumulative error across 12 cycles terr (12per) -269 269 -242 242 -215 215 -188 188 ps cumulative error across n = 13, 14, .....49, 50 cycles terr (nper) terr(nper)min = ( 1 + 0.68ln(n)) * jit(per)min terr(nper)max = ( 1 + 0.68ln(n)) * jit(per)max ps 24 data timing dqs, dqs# to dq skew, per group, per access tdqsq - 200 - 150 - 125 - 100 ps 13 dq output hold time from dqs, dqs# tqh 0.38 - 0.38 - 0.38 - 0.38 - tck (avg) 13, b dq low-impedance time from ck, ck# tlz(dq) - 800 400 - 600 300 - 500 250 - 450 225 ps 13, 14, a dq high impedance time from ck, ck# thz(dq) - 400 - 300 - 250 - 225 ps 13, 14, a timing parameters by speed bin (continued) note: the following general notes from page 57 apply to table : a ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 parameter symbol min max min max min max min max units notes rev. 0.5 /sep 2007 52 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds(base) 75 25 tbd tbd ps d, 17 data hold time from dqs, dqs# referenced to vih(dc) / vil(dc) levels tdh(base) 150 100 tbd tbd ps d, 17 data strobe timing dqs,dqs# differential read preamble trpre 0.9 note 0.9 note 0.9 note 0.9 note tck (avg) 13, 19 b dqs, dqs# differential read postamble trpst 0.3 note 0.3 note 0.3 note 0.3 note tck (avg) 11, 13, b dqs, dqs# differential output high time tqsh 0.38 - 0.38 - 0.38 - 0.38 - tck (avg) 13, b dqs, dqs# differential output low time tqsl 0.38 - 0.38 - 0.38 - 0.38 - tck (avg) 13, b dqs, dqs# differential write preamble twpre 0.9 - 0.9 - 0.9 - 0.9 - tck (avg) dqs, dqs# differential write postamble twpst 0.3 - 0.3 - 0.3 - 0.3 - tck (avg) dqs, dqs# rising edge output access time from rising ck, ck# tdqsck - 400 400 - 300 300 - 255 255 - 225 225 ps 13, a dqs and dqs# low- impedance time (referenced from rl - 1) tlz(dqs) - 800 400 - 600 300 - 500 250 - 450 225 ps 13, 14, a dqs and dqs# high- impedance time (referenced from rl + bl/2) thz(dqs) - 400 - 300 - 250 - 225 ps 13, 14 a dqs, dqs# differential input low pulse width tdqsl 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck (avg) dqs, dqs# differential input high pulse width tdqsh 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck (avg) dqs, dqs# rising edge to ck, ck# rising edge tdqss - 0.25 0.25 - 0.25 0.25 - 0.25 0.25 - 0.25 0.25 tck (avg) c timing parameters by speed bin (continued) note: the following general notes from page 57 apply to table : a ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 parameter symbol min max min max min max min max units notes rev. 0.5 /sep 2007 53 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp dqs, dqs# falling edge setup time to ck, ck# rising edge tdss 0.2 - 0.2 - 0.2 - 0.2 - tck (avg) c dqs, dqs# falling edge hold time from ck, ck# rising edge tdsh 0.2 - 0.2 - 0.2 - 0.2 - tck (avg) c command and address timing dll locking time tdllk 512 - 512 - 512 - 512 - nck internal read command to precharge command delay trtp max (4nck, 7.5ns) - max (4nck, 7.5ns) - max (4nck, 7.5ns) - max (4nck, 7.5ns) -e delay from start of internal write transaction to internal read command twtr max (4nck, 7.5ns) - max (4nck, 7.5ns) - max (4nck, 7.5ns) - max (4nck, 7.5ns) -e, 18 write recovery time twr 15 - 15 - 15 - 15 - ns e mode register set command cycle time tmrd 4 - 4 - 4 - 4 - nck mode register set command update delay tmod max (12nck , 15ns) - max (12nck , 15ns) - max (12nck , 15ns) - max (12nck , 15ns) - act to internal read or write delay time trcd refer to table on pages 46 to pages 49 e pre command period trp refer to table on pages 46 to pages 49 e act to act or ref command period trc refer to table on pages 46 to pages 49 e cas# to cas# command delay tccd 4 - 4 - 4 - 4 - nck auto precharge write recovery + precharge time tdal(min) wr + roundup(trp / tck(avg)) nck end of mpr read burst to msr for mpr(exit) tmprr 1 - 1 - 1 - 1 - nck 22 active to precharge command period tras see ?10. standard speed bins? on page 46. e active to active command period for 1kb page size trrd max (4nck , 10ns) - max (4nck , 7.5ns) - max (4nck, 6ns) - max (4nck, 6ns) -e active to active command period for 2kb page size trrd max (4nck, 10ns) - max (4nck, 10ns) - max (4nck, 7.5ns) - max (4nck, 7.5ns) -e four activate window for 1kb page size tfaw 40 - 37.5 - 30 - 30 - ns e timing parameters by speed bin (continued) note: the following general notes from page 57 apply to table : a ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 parameter symbol min max min max min max min max units notes rev. 0.5 /sep 2007 54 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp four activate window for 2kb page size tfaw 50 - 50 - 45 - 40 - ns e command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) 200 125 65 tbd ps b, 16 command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels tih(base) 275 200 140 tbd ps b, 16 command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) ac150 - - - - 65+125 tbd+ 125 ps b, 16, 27 calibration timing power-up and reset calibration time tzqinit 512 - 512 - 512 - 512 - nck normal operation full calibration time tzqoper 256 - 256 - 256 - 256 - nck normal operation short calibration time tzqcs 64 - 64 - 64 - 64 - nck 23 reset timing exit reset from cke high to a valid command txpr max (5nck, trfc (min) + 10ns) - max (5nck, trfc (min) + 10ns) - max (5nck, trfc (min) + 10ns) - max (5nck, trfc (min) + 10ns) - self refresh timings exit self refresh to commands not requiring a locked dll txs max (5nck, trfc (min) + 10ns) - max (5nck, trfc (min) + 10ns) - max (5nck, trfc (min) + 10ns) - max (5nck, trfc (min) + 10ns) - exit self refresh to com-mands requiring a locked dll txsdll tdllk (min) - tdllk (min) - tdllk (min) - tdllk (min) -nck minimum cke low width for self refresh entry to exit timing tckesr tcke (min) + 1 nck - tcke (min) + 1 nck - tcke (min) + 1 nck - tcke (min) + 1 nck - valid clock requirement after self refresh entry (sre) or power- down entry (pde) tcksre max (5 nck, 10 ns) - max (5 nck, 10 ns) - max (5 nck, 10 ns) - max (5 nck, 10 ns) - timing parameters by speed bin (continued) note: the following general notes from page 57 apply to table : a ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 parameter symbol min max min max min max min max units notes rev. 0.5 /sep 2007 55 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp valid clock requirement before self refresh exit (srx) or power- down exit (pdx) or reset exit tcksrx max (5 nck, 10 ns) - max (5 nck, 10 ns) - max (5 nck, 10 ns) - max (5 nck, 10 ns) - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp max (3nck, 7.5ns) - max (3nck, 7.5ns) - max (3nck, 6ns) - max (3nck, 6ns) - exit precharge power down with dll frozen to commands requiring a locked dll txpdll max (10nck , 24ns) - max (10nck, 24ns) - max (10nck, 24ns) - max (10nck , 24ns) -2 cke minimum pulse width tcke max (3nck 7.5ns) - max (3nck, 5.625ns) - max (3nck, 5.625ns ) - max (3nck, 5ns) - command pass disable delay tcpded 1 - 1 - 1 - 1 - nck power down entry to exit timing tpd tcke (min) 9 * trefi tcke (min) 9 * trefi tcke (min) 9 * trefi tcke (min) 9 * trefi 15 timing of act command to power down entry tactpden 1 - 1 - 1 - 1 - nck timing of pre or prea command to power down entry tprpden 1 - 1 - 1 - 1 - nck timing of rd/rda command to power down entry trdpden rl + 4 + 1 - rl + 4 + 1 - rl + 4 + 1 - rl + 4 + 1 - nck timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden wl+4+ (twr / tck (avg)) - wl 4 + (twr / tck (avg)) - wl+4 + (twr / tck (avg)) - wl+4 + (twr / tck (avg)) -nck9 timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden wl+4+ wr + 1 - wl+4+ wr+ 1 - wl+4 + wr + 1 - wl+4+ wr + 1 -nck10 timing parameters by speed bin (continued) note: the following general notes from page 57 apply to table : a ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 parameter symbol min max min max min max min max units notes rev. 0.5 /sep 2007 56 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp timing of wr command to power down entry (bc4mrs) twrpden wl+2+ (twr / tck (avg)) - wl+2+ (twr / tck (avg)) - wl+2 + (twr / tck (avg)) - wl+2+ (twr / tck (avg)) -nck9 timing of wra command to power down entry (bc4mrs) twrapden wl+2 + wr + 1 - wl + 2 + wr + 1 - wl + 2 + wr + 1 - wl+2 + wr + 1 -nck10 timing of ref command to power down entry trefpden 1 - 1 - 1 - 1 - nck , timing of mrs command to power down entry tmrspden tmod (min) - tmod (min) - tmod (min) - tmod (min) - odt timings odt high time without write command or with write command and bc4 odth4 4 - 4 - 4 - 4 - nck odt high time with write command and bl8 odth8 6 - 6 - 6 - 6 - nck asynchronous rtt turn-on delay (power-down with dll frozen) taonpd 1 9 1 9 1 9 1 9 ns asynchronous rtt turn-off delay (power- down with dll fro- zen) taofpd 1 9 1 9 1 9 1 9 ns rtt turn-on taon -400 400 -300 300 -250 250 -225 225 ps 7, a rtt_nom and rtt_wr turn-off time from odtloff reference taof 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tck (avg) 8, a rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tck (avg) a write leveling timings first dqs/dqs# rising edge after write leveling mode is programmed twlmrd 40 - 40 - 40 - 40 - nck 3 dqs/dqs# delay after write leveling mode is programmed twldqsen 25 - 25 - 25 - 25 - nck 3 timing parameters by speed bin (continued) note: the following general notes from page 57 apply to table : a ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 parameter symbol min max min max min max min max units notes rev. 0.5 /sep 2007 57 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp write leveling setup time from rising ck, ck# crossing to rising dqs, dqs# crossing twls 325 - 245 - 195 - tbd - ps write leveling hold time from rising dqs, dqs# crossing to rising ck, ck# crossing twlh 325 - 245 - 195 - tbd - ps write leveling output delay twlo 0 9 0 9 0 9 0 7.5 ns write leveling output error twloe 0 2 0 2 0 2 0 2 ns timing parameters by speed bin (continued) note: the following general notes from page 57 apply to table : a ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 parameter symbol min max min max min max min max units notes rev. 0.5 /sep 2007 58 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 0.1 jitter notes specific note a when the device is op erated with input clock jitter, this parameter needs to be derated by the actual terr(mper), act of the input cloc k, where 2 <= m <=12.(output deratings are relative to the sdram input cl ock.) for example, if the measured jitter into a ddr-800 sdram has terr(mper),act,min = -172 ps and terr(mper),act,max =+ 193 ps, then t dqsck,min(derated) = tdqsck,min - terr(mper),act,max = -400 ps - 193 ps = - 593 ps and tdqsck,max(derated) = tdqsck,max - te rr(mper),act,min = 400 ps+ 172 ps = + 572 ps. similarly, tlz(dq) for ddr3-800 dera tes to tlz(dq),min(de rated) = - 800 ps - 193 ps = - 993 ps and tlz(dq),max(derated) = 400 ps + 172 ps = + 572 ps. ( caution on the min/max usage!) note that terr(mper),a ct,min is the minimum measured value of terr(nper) where 2 <= n <=12, and terr(mper),act,max is the maximum measured value of terr(nper) where 2 <= n <= 12 specific note b when the device is op erated with input clock jitter, this parameter needs to be derated by the actual tjit(per),act of the input clock. ( output deratings are relative to the sdram input clock. ) for example, if the measured jitter into a ddr3-800 sdram has tck(avg),act = 2500 ps, tjit(p er),act,min = - 72 ps and tjit(per),act,max = + 93 ps, then trpre,min(derated) = trpre,min + tjit (per),act,min = 0.9 x tck(avg),act + tjit(per),act,min(derated) = trpre,min + tj it(per),act,min = 0.9 x tck(avg),act + tjit(per),act,min = 0.9 x 2500 ps - 72 ps =+ 2178 ps. similarly, tqh,min(derated) = tqh,min + tjit(per),act,min = 0. 38 x tck(avg),act + tjit(per), act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (caution on the min/max usage!) specific note c these parameters are measured fr om a data strobe signal (dqs(l/u), dqs(l/u)#) crossing to its respective clock signal (ck, ck#) crossing. the spec values are not affected by the amount of clock jitter applied (i .e. tjit(per), tjit(cc), etc.), as these are rel- ative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. specific note d these parameters are measured from a data signal (dm(l/u), dq(l/u)0, dq(l/u)1, etc.) transition edge to its respective data st robe signal (dqs(l/u), dqs(l/u)#) crossing. specific note e for these parameters, the ddr3 sdram device supports tnparam [nck] = ru{ tparam [ns] / tck(avg) [ns] }, which is in cl ock cycles, assuming all input clock jitter spec- ifications are satisfied.for example, the device will support tnrp = ru{trp / tck(avg)}, which is in clock cycles, if all input clock ji tter specifications are met. this means: for ddr3-800 6-6-6, of which tr p = 15ns, the device will suppor t tnrp = ru{trp / tck(avg)} = 6, as long as the input clo ck jitter specifications are met, i.e. precharge command at tm and active command at tm+6 is valid even if (tm+6 - tm) is less than 15ns due to input clock jitter. specific note f these parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous tim- ing holds at all times. (min and max of spec values are to be used fo r calculations in ta b l e . rev. 0.5 /sep 2007 59 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp timing parameter notes 1. actual value dependant upon measurement level definitions which are tbd. 2. commands requiring a locked dll are: read (and rap) and synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in mode register. 5. value must be rounded-up to next higher integer value. 6. there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. 7. for definition of rtt turn-on time taon see 4.2.2 ?timing parameters? on page 93. 8. for definition of rtt turn-off time taof see 4.2.2 ?timing parameters? on page 93. 9. twr is defined in ns, for calculation of twrpden it is necessary to round up twr / tck to the next integer. 10. wr in clock cycles as programmed in mr0. 11. the maximum postamble is bound by thzdqs(max) 12. output timing de ratings are relative to the sdram input clock. when the device is operated with input clock jitter, this parameter needs to be derated by t.b.d. 13. value is only valid for ron34 14. single ended signal parameter. refer to chapter rev. 0.5 /sep 2007 60 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp where tsens = max(drttdt, drondtm) and vsens = max(drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5% / o c, vsens = 0.15% / mv, tdriftrate = 1 o c / sec and vdriftrate = 15 mv / sec, then the interval between zqcs commands is calculated as : 24. n = from 13 cycles to 50 cycles. 25. tch(abs) is the absolute instantaneous clock high pulse wi dth, as measured from one risi ng edge to the following fall ing edge. 26. tcl(abs) is the absolute instantaneou s clock low pulse width, as measured from one falling edge to the following rising edge. 27. the tis(base) ac150 specifications are adjusted from the ti s(base) specification by adding an additional 100 ps of der ating to accommodate for the lowe r alternate threshold of 150 mv and anothe r 25 ps to account for the earlier refer ence point [(175 mv - 150 mv) / 1 v/ns]. address / command setup, hold and derating for all input signals the total tis (setup time) and tih (hold time) required is calculated by adding the data sheet tis(base) and tih(base) value (see table 1) to the tis and tih derating value (see table 2) respectively. example: tis (total setup time) = tis(base) + tis setup (tis) nominal slew rate for a rising signal is de fined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac) min. setup (tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded ?v ref(dc) to ac region?, use nominal slew rate for derating value (see figure 2). if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc leve l is used for derating value (see figure 4). hold (tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of v ref(dc) . hold (tih) nominal slew rate for a falling signal is defined as the slew rate between the last cross- ing of vih(dc)min and the first crossing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between shaded ?dc to v ref(dc) region?, use nominal slew rate for derating va lue (see figure 3). if the actual signal is ear- lier than the nominal slew rate line anywhere between shaded ?dc to v ref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for derating value (see figure 4). for a valid transition the input signal has to remain above/below v ih/il(ac) for some time t vac (see table 4). zqcorrection (tsens x tdriftrate)+ ( vsens x vdriftrate) -------------------------- ------------------------------ ----------------------------- ----------------------- 0.5 (1.5 x 1)+(0.15 x 15) ------------------------------- ----------------------- 0 . 1 3 3 1 2 8 m s == rev. 0.5 /sep 2007 61 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp although for slow slew rates the total setup time might be negative (i.e. a valid input si gnal will not have reached v ih/il(ac) at the time of the rising clock transition) a valid input si gnal is still required to complete the transition and reach v ih/il(ac) . for slew rates in between the values listed in table 2, the derating values may obtained by linear interpolation. these values are typically not subject to production te st. they are verified by design and characterization. table 1 ? add/cmd setup and hold base-values for 1v/ns note: - (ac/dc referenced for 1v/ns dq-slew rate and 2 v/ns dqs slew rate) - the tis(base) ac150 specifications are adjusted fr om the tis(base) specification by adding an additional 100 ps of derating to accommodate for the lower altern ate threshold of 150 mv and another 25 ps to account for the earlier reference point [(175 mv - 150 mv) / 1 v/ns] unit [ps] ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 reference tis(base) 200 125 65 tbd v ih/l(ac) tih(base) 275 200 140 tbd v ih/l(dc) tih(base)ac150 - - 65 + 125 tbd + 125 v ih/l(dc) rev. 0.5 /sep 2007 62 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp table 2 ? derating values ddr3-800/1066/1333/1600 tis/tih - ac/dc based table 3 ? derating values ddr3-800/1066/1333/1600 tis/tih - ac/dc based tis, tih derating in [ps] ac/dc based ac175 threshold -> vih(ac) = vref(dc) + 175mv, vil(ac)=vref(dc) - 175mv ck,ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd / add slew rate v/ns 2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.55934593459 34 67427550835891689984 1.00 0 0 0 0 0 8 8 1616242432344050 0.9-2 -4 -2 -4 -2 -4 6 4 1412222030303846 0.8 -6 -10 -6 -10 -6 -10 2 -2 10 6 18 14 26 24 34 40 0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34 0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10 0.4 -62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10 tis, tih derating in [ps] ac/dc based alternate ac150 threshold -> vih(ac) = vr ef(dc) + 150mv, vil(ac)=vref(dc) - 150mv ck,ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd / add slew rate v/ns 2.07550755075 50 83589166997410784115100 1.55034503450 34 58426650745882689084 1.00 0 0 0 0 0 8 8 1616242432344050 0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46 0.8 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40 0.7 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34 0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10 rev. 0.5 /sep 2007 63 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp table 4 ? required time t vac above vih(ac) {below vil(ac)} for valid transition slew rate [v/ns] t vac @ 175 mv [ps] t vac @ 150 mv [ps] min max min max > 2.0 75 - 175 - 2.0 57 - 170 - 1.5 50 - 167 - 1.0 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 150 - < 0.5 0 - 150 - rev. 0.5 /sep 2007 64 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp figure 1 ? illustration of nominal slew rate and t vac for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock). v ss setup slew rate setup slew rate rising signal falling signal tf tr v ref(dc) - v il(ac) max tf = v ih(ac) min - v ref(dc) tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal nominal slew rate vref to ac region vref to ac region tvac tvac slew rate tdh tds dqs dqs# tdh tds ck# ck tis tih tis tih note: clock and strobe are drawn on a different time scale. rev. 0.5 /sep 2007 65 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp figure 2 ? illustration of nomi nal slew rate for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock). v ss hold slew rate hold slew rate falling signal rising signal tr tf v ref(dc) - v il(dc) max tr = v ih(dc) min - v ref(dc) tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region tdh tds dqs dqs# tdh tds ck# ck tis tih tis tih note: clock and strobe are drawn on a different time scale. rev. 0.5 /sep 2007 66 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp figure 3 ? illustration of tangent line for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock) v ss tdh setup slew rate setup slew rate rising signal falling signal tf tr tangent line[ v ref(dc) - v il(ac) max] tf = tangent line[v ih(ac) min - v ref(dc) ] tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tvac tvac dqs dqs# tdh tds ck# ck tis tih tis tih note: clock and strobe are drawn on a different time scale. rev. 0.5 /sep 2007 67 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp figure 4 ? illustration of tangent line for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock) v ss hold slew rate tf tr tangent line [ v ih(dc) min - v ref(dc) ] tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - v il(dc) max ] tr = rising signal tdh tds dqs dqs# tdh tds ck tis tih tis tih n o t e: cl oc k an d st ro b e are d rawn on a different time scale. ck# rev. 0.5 /sep 2007 68 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp data setup, hold and slew rate derating for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the data sheet tds(base) and tdh(base) value (see table 5) to the dtds and dtdh (see table 6) derating value respectively. example: tds (total setup time) = tds(base) + dtds. setup (tds) nominal slew rate for a ri sing signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac) min. setup (tds) nominal slew rate for a falling sign al is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il(ac) max (see figure 5). if the actual sign al is always earlier than the nomi- nal slew rate line between shaded ?v ref(dc) to ac region?, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc le vel is used for derating value (see figure 7). hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il(dc) max and the first crossing of v ref(dc) . hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc) min and the first crossing of v ref(dc) (see figure 6). if the actual signal is always later than the nominal slew rate line between shaded ?dc level to v ref(dc) region?, use nominal slew rate for dera ting value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for derating value (see figure 7). for a valid transition the input si gnal has to remain above/below v ih/il(ac) for some time t vac (see table 7). although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached v ih/il(ac) at the time of the rising clock transition) a valid input sign al is still required to complete the transition and reach v ih/il(ac) . for slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verifi ed by design and characterization. table 5 ? data setup and hold base-values note: (ac/dc referenced for 1v/ns dq-sle w rate and 2 v/ns dqs-slew rate) units [ps] ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 reference tds(base) 75 25 -10 tbd v ih/l(ac) tdh(base) 150 100 65 tbd v ih/l(dc) rev. 0.5 /sep 2007 69 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp table 6 ? derating values ddr3-800/1066 tds/tdh - ac/dc based table 7 ? required time t vac above vih(ac) {below vil(ac)} for valid transition tds, dh derating in [ps] ac/dc based a a.cell contents shaded in red are defined as ?not supported?. dqs, dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 2.0 88 50 88 50 88 50 - - - - - - - - - - 1.5 59 34 59 34 59 34 67 42 - - - - - - - - 1.0 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - -2 -4 -2 -4 6 4 14122220 - - - - 0.8 - - - - -6 -10 2 -2 10 6 18 14 26 24 - - 0.7 - - - - - - -3 -8 5 0 13 8 21 18 29 34 0.6 - - - - - - - - -1 -10 7 -2 15 8 23 24 0.5 - - - - - - - - - --11-16-2-6 510 0.4 - - - - - - - - - - - - -30 -26 -22 -10 slew rate [v/ns] t vac [ps] min max > 2.0 75 - 2.0 57 - 1.5 50 - 1.0 38 - 0.9 34 - 0.8 29 - 0.7 22 - 0.6 13 - 0.5 0 - < 0.5 0 - rev. 0.5 /sep 2007 70 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp figure 5 ? illustration of nominal slew rate and t vac for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock). v ss setup slew rate setup slew rate rising signal falling signal tf tr v ref(dc) - v il(ac) max tf = v ih(ac) min - v ref(dc) tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal nominal slew rate vref to ac region vref to ac region tvac tvac slew rate tdh tds dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale. rev. 0.5 /sep 2007 71 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp figure 6 ? illustration of nomi nal slew rate for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock). v ss hold slew rate hold slew rate falling signal rising signal tr tf v ref(dc) - v il(dc) max tr = v ih(dc) min - v ref(dc) tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region tdh tds dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale. rev. 0.3 / may 2007 72 figure 7 ? illustration of tangent line for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock) v ss tdh setup slew rate setup slew rate rising signal falling signal tf tr tangent line[ v ref(dc) - v il(ac) max] tf = tangent line[v ih(ac) min - v ref(dc) ] tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tvac tvac dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale. rev. 0.3 / may 2007 73 figure 8 ? illustration of tangent line for hold time t dh (for dq with respect to strobe) and t ih (for add/ cmd with respect to clock) v ss hold slew rate tf tr tangent line [ v ih(dc) min - v ref(dc) ] tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - v il(dc) max ] tr = rising signal tdh tds dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale. rev. 0.5 /sep 2007 74 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 12. package dimensions 12.1 package dimension(x4/x8) ; 82ball fine pitch ball grid array outline a1 ball mar k b a 1.0000.100 2.1000.100 0.800 x 10 = 8.000 0.800 1 2 3 7 8 9 0.800 x 12 = 9.600 0.800 2.4000.100 1.60 0 1.60 0 ? 0.15 82 x 0.4500.050 m c a b ball view d c f e h g k j m l n 0.340 0.050 1.100 0.100 0.10 c 1 seating plance c 0.10 c 2-r0.130 max 0.1500.050 side view a 10.0000.100 a1 corner index area (2.500) 0.15 b (4x) 14.4000.100 (3.600) 3.0 x 5.0 min flat area 1 top view rev. 0.5 /sep 2007 75 hy5tq1g431znfp hy5tq1g831znfp hy5tq1g631znfp 12.2 package dimension(x16) ; 100ball fine pitch ball grid array outline a1 i ndex mark b a 1.0000.100 2. 10 0 0 . 10 0 0.800 x 10 = 8.000 0.800 1 2 3 7 8 9 0.800 x 15 = 12.000 0.400 1.2000.100 1. 6 0 0 1. 6 0 0 0.15 10 0 x 0.4500.050 m c a b ball view d c f e h g k j m l p n r t 2-r0.130 max 0.1500.050 side view 0.10 c 1 seating plance c 0.10 c a 10.0000.100 a1 corner index area (2.500) 0.15 b (4x) 14 . 4 0 0 0 . 10 0 (3.600) 3.0 x 5.0 mi n flat area 1 top view |
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